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ASIC-omkostninger kan reduceres markant med nye referencedesigns

ASIC-omkostninger kan reduceres markant med nye referencedesigns

Det engelske ASIC-designfirma Sondrel lancerer en familie af referencedesigns, der kan reducere designomkostninger og -tid i et ASIC-projekt med op til 30 procent (in english).

Sondrel has launched a family of reference designs that could reduce design costs, risk and time by up to 30% compared to starting from scratch. The company has drawn on its experience of designing hundreds of ASICs to create a set of key reference designs that each provide a fast design time for high growth markets.

- In a given application area, there is always considerable duplication in the design of each ASIC as there is a lot of communality in the interconnections and supporting IP that forms the architecture of the device, explains Graham Curren, Sondrel’s CEO.


- Rather than start from scratch with each new design, we have created reference designs that distils our experience of designing the architecture for such chips to create reusable IP platforms. Onto this, we add the customer’s IP with some customisation to create a bespoke solution for that customer. This reduces the overall design costs and risk as our IP platform is tested and ready to use which also means that the time to market is redced as well. We estimate that this approach, which we are calling Architecting the future, will provide time and cost savings of up to 30% for customers.

Ian Walsh, Sondrel’s VP World-wide Sales, adds:

- Potential customers for ASIC are often concerned that a custom ASIC will be very expensive. Our semi-custom, reusable IP platforms not only reduce costs but also makes it much easier to give indicative costs for customers right at the start so that they can see how cost effective and affordable our solution will be. Our experience with each reference design means that we can estimate the ballpark costs for design, IP licensing, foundry, test, qualification and packaging right through to the total cost per unit. Just what is needed for budgeting a new project and deciding its viability.

Sondrel will be releasing more than five IP platforms in this family through the year, that target advanced nodes to provide cost effective devices. Two will be targeted at ADAS while the other three have scalable amounts of processing power that address the needs of different application areas. To further reduce risk and time to market, Sondrel offers a full turnkey service that turns designs into fully tested, shipping silicon.

The first architecture being announced is the SFA 200. This design is targeted at fixed and mobile (battery powered) applications, such as Smart Home, Smart Metering, Sensor Fusion and other occasions where a compact chip can add processing ‘smarts’ by providing local end-point data processing for data collection and analysis along with inference processing. It can be arrayed to implement scalable processing applications if required.

The datasheet can be downloaded at https://www.sondrel.com/sfa-200-datasheet
1/3 2021
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