FPGA, CPLD, ASIC og EDA

 

Validering af nye AMD-processorer med 13 mia. transistorer på bare ni timer

Synopsys' værktøj til fysisk chipverifikation, IC Validator, er ved brug af Microsoft Azure cloud-miljøet brugt til at validere AMD Radeon Pro VII GPU med 13 mia. transistorer på bare ni timer (in english).

Synopsys has announced that its IC Validator physical verification solution running on Microsoft Azure completed a verification run of the AMD Radeon Pro VII GPU, which includes more than 13 billion transistors, in less than nine hours. The collaboration was powered by Azure HBv2 virtual machines, using the 2nd Generation AMD EPYC processors.


IC Validator utilized unique elastic CPU management technology to realize up to 40 percent savings in compute resources, achieving lower cost of ownership on cloud and ensuring resource availability for other critical jobs during tapeout.



- At AMD, on-time execution of our products is critical to supporting our goal of providing leadership products in high-performance computing, says Mydung Pham, corporate vice president, Silicon Design Engineering, AMD.

- The AMD EPYC processor-based Azure HBv2 virtual machines are a great fit for high-performance workloads, and we are excited to see Synopsys use them to power its IC Validator solution, helping customers validate hardware and chip design in a short timeframe.
 
- Increasing design sizes and complexity in silicon design is driving the industry to think about the compute infrastructure differently, says Mujtaba Hamid, head of product, Silicon, Electronics and Gaming, at Microsoft Azure.
- Taping out chips with exponentially growing transistor counts, on schedule, remains an imperative for the industry. Azure enables silicon design teams to do so in a secure and cost-effective manner through an EDA-optimized, scalable cloud infrastructure. 

IC Validator is a comprehensive and highly scalable physical verification solution, that includes DRC, LVS, programmable electrical rule checks (PERC), dummy metal fill, and design-for-manufacturability (DFM) enhancement capabilities.

IC Validator is architected for high performance and scalability, which maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing across multiple machines to provide scalability benefits that extend to thousands of CPUs.

- Our focus is to provide our customers the fastest path to physical signoff closure, both in on-premise and in cloud environments, explains Raja Tabet, senior vice president of engineering, Design Group at Synopsys.

- With IC Validator, the industry's fastest physical verification solution, our customers can leverage Microsoft Azure cloud using AMD EPYC processors to signoff their chips with fast turnaround-time while ensuring optimal use of compute resources.
20/8 2020
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