Embedded SRAM med rekordlavt standby forbrug

Embedded SRAM med rekordlavt standby forbrug

Renesas annnocerer embedded SRAM med industriens laveste standby effektforbrug på 13,7 nW/Mbit og 1,84 ns højhastigheds readout (in english).

Renesas Electronics has announced the successful development of a new low-power SRAM circuit technology that can be embedded in application specific standard products (ASSPs) for Internet of Things (IoT), home electronics, and healthcare applications.

The new technology provides a function for switching dynamically, with a low power overhead, between active operation, in which the CPU core performs read and write operations of the embedded SRAM, and the standby mode, in which the stored data is retained.

Renesas applied its in-house 65 nanometer (nm) node silicon on thin BOX process for the prototype development of embedded SRAM. The prototype SRAM achieves at the same time both the high-speed readout time of 1.8 ns during active operation and the ultra-low power consumption of 13.7 nW/Mbit in standby mode.

The SRAM achieves the industry's lowest standby mode power consumption characteristics, which is only one-thousand of the power consumption during standby mode, by using dynamic substrate back bias control, taking advantage of the SOTB structure.

Recently, in the rapidly growing IoT market, all applications will be connected wirelessly, and thus there are strong desires for either battery free operation, which uses natural energy sources such as light, vibration, or heat, and lower power consumption for longer battery life. In addition, when a longer battery life is achieved, battery replacement will no longer be required, which enables applications to be maintenance free.

At the same time, achieving miniaturization of end products is essential for the development of IoT applications. Reduction of the ASSP’s power consumption to at least one order of magnitude would enable miniaturization as it reduces the currently used battery capacity.

As an effort to reduce the power consumption in ASSPs for the IoT, there is a technique in which the application is operated intermittently, normally being in the standby mode and only going to active mode when data processing is required. In particular, the most commonly used procedure to reduce power consumption in standby mode is to cut off power to the circuit after saving any necessary data either to an external device or to internal nonvolatile memory.

Although this method is effective when wait times are relatively long, in systems that frequently iterate the switching between the active- and standby mode, the saving of data to nonvolatile memory and the restart operation becomes a significant overhead. There are even cases where, inversely, this actually increases power consumption.

The new technology adopts a method in which the power consumption of the embedded SRAM in standby mode is reduced. This enables intermittent operation to be performed frequently without leading to increased power consumption, thereby making it unnecessary to save data to nonvolatile memory, which leads to improved power efficiency.

Previous Renesas efforts related to embedded SRAM include prototype of embedded SRAM with a 28 nm high-K metal gate (HKMG) structure and a high-performance embedded SRAM with a 16 nm Fin field-effect transistor (FinFET) structure, which both adopt state-of-the-art process technologies.

These embedded SRAM technologies have been adopted in Renesas’ R-Car automotive infotainment system-on-chips (SoCs). Now, to achieve the low-power performance required by IoT, home electronics, and healthcare applications, Renesas developed circuit technology that dynamically controls the substrate bias using the SOTB process technology and enables standby mode leakage current to be reduced to approximately one-thousandth of the power compared to the normal standby mode.
12/6 2017
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