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Altera kombinerer FPGA og ARM processor

Altera løfter sløret for de såkaldte SoC FPGA'er, der kombinerer en dual-core ARM Cortex-A9 MPCore med en FPGA-fabric samt memorycontroller og en række vigtige periferifunktioner (in english).

Altera Corporation has unveiled its family of ARM-based SoC FPGAs, integrating 28-nm Cyclone V and Arria V FPGA fabric, a dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect into a single chip.

These SoC FPGAs inherit ARM’s rich ecosystem of software development tools, debuggers, operating systems, middleware and applications. Users can leverage Altera’s SoC FPGA development flow to quickly create customized ARM-based systems that reduce embedded system board size, power and cost, while boosting performance in a variety of industries, including automotive, industrial, video surveillance, wireless infrastructure, computer and storage.


Altera’s Cyclone V and Arria V SoC FPGAs feature a processor system with a dual-core 800 MHz ARM Cortex-A9 MPCore processor, NEON media processing engine, single/double-precision floating point unit, L1 and L2 caches, ECC-protected memory controllers, ECC-protected scratchpad memory and a wide range of commonly used peripherals.

The processor system can deliver 4,000 DMIPS peak performance for less than 1.8 watts.  The processor system and FPGA fabric are powered independently and can be configured and booted in any order. Once in operation, the FPGA portion can be powered down as needed to conserve system power.

The ARM Cortex-A9 MPCore processor system and FPGA are interconnected by high throughput data paths, providing over 125-Gbps peak bandwidth with integrated data coherency. This level of performance is not possible in two-chip solutions. An integrated single-chip SoC FPGA allows board designers to eliminate the external I/O paths between a processor and an FPGA, providing significant system power savings.

Family of SoC FPGAs

Altera’s family of SoC FPGAs leverage its 28-nm product portfolio, which are tailored to meet customers’ power, performance and cost requirements by innovating in several areas, including process technology, transceiver technology, I/O resources and hard IP. The introduction of Cyclone V and Arria V SoC FPGAs extend the portfolio’s reach into the embedded processing market.

The Cyclone V and Arria V SoC FPGAs are based on a low-power 28-nm process (28LP). These families feature embedded transceivers that operate up to 5-Gbps and 10-Gbps respectively. The FPGA fabric includes variable-precision DSP blocks and up to three ECC-protected memory controllers. A

ltera's Cyclone V SoC FPGAs feature up to 110K logic elements (LEs) and provide the industry's lowest system cost and power, along with performance levels that make the devices ideal for differentiating high-volume applications, including next-generation industrial drive on a chip, advanced driver assistance and video surveillance.

Arria V SoC FPGAs balance cost and performance while delivering the lowest total power for mid-range applications. The devices feature up to 460K LEs and are ideal for meeting the higher performance requirements in applications that include remote radio heads, LTE base stations and multi-function printers.

SoC FPGA development environment

Altera’s SoC FPGAs enable both hardware and software teams to maximize their productivity by using common tools and development flows that support both the Cortex-A9 MPCore processor and the FPGA.

Designers can create custom peripherals and hardware accelerators using Altera’s Quartus II software and integrate them with the processor system using Altera’s Qsys system integration tool. Qsys accelerates the hardware design process by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems.

Qsys automatically generates an FPGA-optimized network-on-a-chip (NoC) interconnect, delivering higher performance, enabling improved design reuse and providing faster verification. Qsys supports industry-standard interfaces including Avalon Memory-Mapped, Avalon Streaming and AMBA AXITM from ARM, enabling users to leverage and reuse IP cores with multiple interfaces in a single design.

Because SoC FPGAs are based on the standard ARM Cortex-A9 MPCore processor, they are compatible with the existing ARM software ecosystem. Software development for systems based on SoC FPGAs can begin immediately on Altera’s SoC FPGA Virtual Target.

Based on proven virtual prototyping solutions from Synopsys, Inc., the SoC FPGA Virtual Target is a PC-based functional simulation of an Altera SoC FPGA development board. The Virtual Target is a binary- and register-compatible, functional equivalent of an SoC FPGA board, ensuring that software developed on the Virtual Target can be moved to the actual board with minimal effort. 

Linux- and VxWorks-enabled and supported by leading ARM ecosystem development tools, the Virtual Target lets embedded software engineers develop their application using familiar tools, maximize legacy code reuse, and gain further productivity from the unparalleled level of target control and target visibility that are critical for complex multicore processor systems development.

 Delivered as a prebuilt, ready-to-use, binary- and register-compatible PC-based simulation model, the SoC FPGA Virtual Target features the same dual-core ARM Cortex-A9 MPCore™ processor and system peripherals found in Altera’s Cyclone V and Arria V SoC FPGAs, along with board-level components, including DDR SDRAM, flash memory, and virtual I/Os.

To enable application software development targeting both the hardened processor system and customer-designed FPGA-based IP, Altera will provide an optional FPGA-in-the-loop extension to the Virtual Target. This extension uses an Altera FPGA development board connected to the PC-based Virtual Target over a PCIe interface.

The Virtual Target and the FPGA-in-the-loop extension together let users add custom peripherals and hardware accelerators to the processor subsystem, create device drivers for them, and integrate with application software prior to final hardware availability. This allows the device-specific firmware and application software to move to the actual hardware with minimal effort. 

The Virtual Target comes with initial support for Linux and VxWorks. Embedded software developers can boot Linux on the Virtual Target right out-of-the-box using a prebuilt Linux kernel image with device driver support for all the major components of the SoC FPGA development board. Free downloads of a prebuilt GNU tool chain and Linux source also are available from Altera. A VxWorks board support package (BSP) will be available this quarter for the Virtual Target, with more BSPs to come for other embedded operating systems.

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