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Send til en ven   Udskriv14/12 2011 kl. 13:46
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ARM Cortex-A9 bryder GHz-muren

Ved brug af Synopsys EDA-værktøjer er det lykkedes Global Unichip at fremstille en dual ARM Cortex-A9 MPcore processor, der opererer ved clockhastighed på over 1 GHz (in english).

Synopsys and Global Unichip Corporation (GUC) has announced that GUC has achieved more than one gigahertz frequency on a dual-core ARM Cortex-A9 MPCore processor with Synopsys IC Compiler, a key component of Synopsys’ Galaxy Implementation Platform. Synopsys’ high performance Galaxy implementation methodology was instrumental in achieving more than one gigahertz frequency with minimum power, while reducing schedule risk.

- As the Flexible ASIC Leader, we serve the highly competitive, smart electronics market, says Jim Lai, president, GUC.
- For our customers, performance, power and time to market are key differentiators. Partnering with Synopsys to combine their leading-edge tools and technologies with our advanced process and low power design expertise has enabled us to strengthen our service offering and address customer demands.


- We faced several challenges to meet the frequency target for our high-end processor core based designs, which motivated us to adopt IC Compiler, says Albert Li, director, Design Development, Design Service Division, GUC.

- Along with Design Compiler Topographical, IC Compiler’s design closure capabilities were critical in closing the frequency gap and helping us tapeout on time. We have standardised this flow for our 40 and 28 nm core hardening needs.

The five-million-gate, dual-core ARM Cortex-A9 processor, intended for high-end digital television chips, was fabricated on a TSMC 40nm low power process. It achieved a signoff frequency of 1 GHz at the worst process corner and 1.3 GHz at the typical process corner, without requiring the use of overdrive voltage.

GUC used the Synopsys Galaxy implementation methodology to overcome the design challenges associated with achieving this level of operating frequency and power, including:
• Sensitivity of high performance designs to memory macro placement, making it difficult to meet timing between the memories and processors
• Placement of register banks for improved frequency and routability, often requiring support for structured placement techniques
• High utilisation in excess of 80 percent, requiring timing and congestion to be managed from the outset, starting with synthesis through place and route
• Tight skew and latency requirements for clock distribution network
Highlights of GUC’s Galaxy implementation flow include:
• Design Compiler Topographical to create a better initial netlist for IC Compiler physical implementation
• IC Compiler’s design planning technology for macro placement, along with its physical datapath technology for optimal placement of register banks
• PrimeTime for tight correlation between implementation and signoff static timing analysis to deliver high performance, low power, correlated results

- Synopsys IC Compiler has been the widely recognised tool of choice for high performance processor design, says Antun Domic, senior vice president and general manager, Implementation Group at Synopsys.

- We have continued to invest in optimisation technology delivering high operating frequency while consuming the lowest power. Our collaboration with GUC and resulting tapeout success at gigahertz-plus speed is strong evidence of our technology delivering winning results.

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