Seneste nyt om:

Seminarer • konferencer
kurser • messer
Send til en ven   Udskriv1/12 2011 kl. 13:07
Send til en ven

Lattice lancerer ny FPGA-familie

Lattice løfter nu sløret for den kommende ECP4 familie af FPGA'er, der sigter mod 'midrange' applikationer (in english).

Lattice Semiconductor has announced the next generation LatticeECP4 FPGA family, with 6 Gbps SERDES in low cost wire-bond packages, powerful DSP Blocks and hard IP-based Communication Engines for cost- and power-sensitive wireless, wireline, video, and computing markets. 

The LatticeECP4 FPGA family builds on the LatticeECP3 family by bringing premium features to mainstream customers while maintaining industry-leading low power and low cost.  The LatticeECP4 devices are ideal for developing mainstream platforms for a variety of applications such as Remote Wireless Radio Heads, Distributed Antenna Systems, Cellular Basestations, Ethernet Aggregation, Switching, Routing, Industrial Networking, Video Signal Processing, Video Transmission and Data Center Computing.

The LatticeECP4 FPGAs contain up to sixteen CEI-compliant 6 Gbps SERDES channels with embedded Physical Coding Sub-layer (PCS) blocks in both low cost wire-bonded and high performance flip chip packages, giving customers the choice to deploy the LatticeECP4 FPGA in chip to chip as well as long haul backplane applications. 

The versatile and configurable SERDES/PCS can be seamlessly integrated with the hardened Communication Engines to economically build complete high bandwidth sub-systems.  The Communication Engines offer up to 10X the power and cost reduction of similar implementations in FPGA fabrics. 

The LatticeECP4 Communication Engines portfolio includes solutions for PCI Express 2.1, multiple 10 Gigabit Ethernet MAC and Tri-speed Ethernet MACs as well as Serial Rapid I/O (SRIO) 2.1.  The combination of SERDES/PCS and Communication Engines is ideal for completing complex serial protocol-based designs with lower cost, power and footprint while accelerating time to market.

Innovative DSP processing

The LatticeECP4 family features powerful digital signal processing (DSP) blocks with 18x18 multipliers, wide ALUs, adder-trees and carry chains for cascadability.  Unique booster logic means each LatticeECP4 DSP block can be equal to four LatticeECP3 DSP blocks, enabling up to 4X the signal processing capability of the previous generation LatticeECP3 devices. 

The flexible 18x18 multipliers can be split into 9x9 or combined into 36x36 to perfectly match customers’ application requirements. Moreover, up to 576 multipliers can be cascaded together to build complex filters for wireless Remote Radio Heads (RRH), MIMO-based RF antenna solutions and video processing applications.

Higher performance and capacity

The LatticeECP4 FPGAs are up to 50% faster than previous generation devices and feature 1066 Mbps DDR3 memory interfaces and 1.25 Gbps LVDS I/Os that are also capable of being provisioned as serial Gigabit Ethernet interfaces. 

The new LatticeECP4family also has 66% more logic resources and 42% more embedded memory to empower design engineers to construct complete systems-on-chip in FPGAs.

- The next generation LatticeECP4 FPGA family offers our customers an unprecedented combination of the premium features, high performance, low cost and low power that is necessary for sophisticated but cost sensitive wireless, wireline, video and computing applications.  Lattice has been a pioneer in providing cutting-edge innovations in economical devices for our customers.  With the LatticeECP4 devices now included in our Lattice Diamond® design software, our customers can begin immediately to build broad-based, lower power platforms to expand their markets, says Sean Riley, Lattice Corporate Vice President and General Manager, Business Group.

Design support for LatticeECP4 FPGAs

Lattice provides intellectual property (IP) cores, development boards and design software for quick launch of design initiatives and rapid time to market.  A range of intellectual property (IP) cores will include CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, SMPTE for serial connectivity, FIR filters, FFT, Reed-Solomon encoders/decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity.

Customers can begin designing with LatticeECP4 FPGAs now using the Lattice Diamond 1.4 beta design software.  Lattice Diamond design software is the new flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enables designers to more quickly target low power, cost sensitive FPGA applications. 

In addition, Lattice Diamond software continues to provide industry-leading features specifically developed for low cost and low power applications.  These include a very accurate power calculator, pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions. 

Relaterede nyheder
Elektronik & Data • Odsgard A/S • Stationsparken 25 • 2600 Glostrup • Tlf: +45 4345 1063