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Send til en ven   Udskriv9/11 2009 kl. 18:25
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Ny dataplane processor (DPU) fra Tensilica

Tensilica introducerer Xtensa LX3, der en højtydende dataplane processor (in english).

Tensilica has introduced  the Xtensa LX3 high-performance dataplane processor (DPU) core optimized for digital signal processing (DSP) and control in the system-on-chip (SOC) dataplane. The Xtensa LX3 DPU offers the industry's widest range of pre-verified DSP options ranging from a simple floating point accelerator to a 16-MAC (multiply accumulator) vector DSP powerhouse.

The base Xtensa LX3 DPU configuration can reach speeds of over 1 GHz in 45nm process technology (45GS) with an area of just 0.044 mm2 and power of 0.015 mW/MHz. When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers over 10 Giga-MACs-per-second performance, running at 625 MHz with a footprint of 0.93mm2 (post place-and-route 45GS) and consuming just 170 mW (including leakage).

The Xtensa LX3 DPU has been fine-tuned with optimized scripts for the latest generation of EDA tools, to deliver even better speed-power-area results than the predecessor Xtensa LX2 cores.  When comparing functionally equivalent configurations of the Xtensa LX3 DPU versus the prior generation Xtensa LX2 DPU, the new Xtensa LX3 processor delivers up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power using identical process technologies and libraries.
 
- The Xtensa LX3 processor, Tensilica's flagship product, provides significant speed and power improvements to enable efficient digital signal processing and control processing in SOC or mixed signal devices, says  Jack Guedj, Tensilica's president and CEO. 

- We've invested heavily in our DPU technology to make it smaller, easier to use, and up to 20 percent faster, providing designers with the performance levels and connectivity expected from custom RTL blocks along with the programmability and debug benefits of conventional processors. And since Xtensa LX3 cores are pre-verified modules, it significantly reduces design risks for dataplane design compared to traditional custom hardware RTL design approaches.

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