Medieplan 2012 DK
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Udskriv9/3 2011 kl. 13:37EFEC IP-kerner til 100G applikationer
Altera lancerer første integrerede 100G EFEC IP-løsning til FPGA-baseret 'Enhanced Forward Error Correction' (in english).
Altera Corporation announces availability of the industry’s first integrated, enhanced forward error correction (EFEC) IP cores optimised for high performance Stratix IV and Stratix V series FPGAs.
The EFEC7 and EFEC20 are multi-dimensional IP cores developed by Altera’s Newfoundland Technology Centre (formerly Avalon Microelctronics) and specifically designed for 100G applications such as metro and long-haul optical transport networks (OTN).
Service providers today are upgrading their 10G metro and long-haul OTN networks to 100G speeds to support growing bandwidth requirements for video data, as well as planning for 400G in the future. In addition, these network backbones must operate over 25-50 percent longer fiber spans, while providing lower power, cost, and latency. Altera’s EFEC IP cores provide the required performance and error free delivery over longer distances.
- With the combined forecast of the 10G, 40G, and 100G transceiver and transponder market expected to grow to over $2 billion worldwide in 2014(1), we are well positioned to provide high-performance flexible silicon platforms with customizable IP, says Don Faria, senior vice president, Altera Communication and Broadcast Business Division.
- Being the first to deliver an integrated, single source 100G solution allows us to ramp-up quickly to meet market demand for the next-generation optical networks.
Altera’s EFEC7 and EFEC20 are ultra high gain, hard decision FEC cores that enhance 100G networks and provide the smallest FPGA-based EFEC implementation available in the industry today. The EFEC7 and EFEC20 leverage a Streaming Turbo Product Code BCH code (SPC-BCH) for best in class gain at the standard G.709.
At 7 percent and 20 percent overhead ratio respectively, the EFECs provide increased transmission distance and lower transmission power. Altera’s SPC-BCH EFECs efficiently solve the implementation complexity issues associated with 100G data rates.
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