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Send til en ven   Udskriv19/10 2009 kl. 16:48
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Komplet wireless subsystem

National Semiconductor introducuerer komplet subsystem af en 'wireless basestation IF sampling receiver' (in english). 

National Semiconductor has announced the availability of an intermediate frequency (IF) sampling receiver reference design for multi-carrier, multi-standard wireless basestations addressing GSM/EDGE, WCDMA, LTE and WiMAX standards.

The subsystem reference design kit gives radio designers the necessary technical material – reference design board, software, schematic, bill of materials (BOM) and Gerber files – to accelerate the design and development of high-performance radio receivers.


The SP16160CH1RB reference design board facilitates evaluation of the IF receive signal path performance under a variety of input conditions. When combined with a low-noise, high-linearity RF front-end and sufficient IF filtering, the reference design enables high sensitivity receivers that exceed the stringent multi-carrier GSM requirements in both normal and blocking conditions. Improved receiver sensitivity translates to enhanced basestation capacity and coverage, allowing service providers to reach more customers and deliver a higher quality of service.

The SP16160CH1RB delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF. With the digitally-controlled variable gain amplifier (DVGA) set at a maximum gain of 22 dB, the sensitivity is limited primarily by the noise contribution of the DVGA.

In the presence of a strong blocker, with the DVGA gain set at 12 dB and blocker level kept at 1.6 dBm input to the ADC, the SP16160CH1RB board delivers sensitivity of -86 dBm. In this blocking condition, the receiver sensitivity is determined by the ADC’s high spurious-free dynamic range (SFDR). 

The SP16160CH1RB operates from a single 5V supply and includes the dual-channel ADC16DV160 16-bit, 160 mega-samples per second (MSPS) pipeline ADC, dual-channel LMH6517 DVGA, and LMK04031B clock jitter cleaner.

The overall performance of the reference design is enabled by the high dynamic performance of the ADC, the low-noise and high-linearity of the DVGA and ultra-low rms jitter of the clock jitter cleaner. The ADC16DV160 delivers a signal-to-noise ratio (SNR) of 76.3 dBFS and SFDR of 91.2 dBFS at 192 MHz input IF, while the LMH6517 provides a noise figure of 6 dB and OIP3 of 45 dBm, and the LMK04031B clock jitter cleaner offers near 150 fsec of rms clock jitter. 

To simplify evaluation of the SP16160CH1RB, National offers the WaveVision 5.1 data capture board and WaveVision 5 software, which enables data capture and analysis, as well as complete programmable configuration of the ADC16DV160 and LMH6517 via a common serial peripheral interface (SPI) bus. Included with the SP16160CH1RB board, is a PIC loader board for configuring the LMK04031B.

Available now, the SP16160CH1RB subsystem reference design kit is priced at $995 each. For more information or to order the design kit, visit http://www.national.com/rd/RDhtml/RD-179.html. 

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