Analog, mixed-signal

 

Differentielle clock-buffere understøtter hastigheder på op til 400Gbit/s

Differentielle clock-buffere understøtter hastigheder på op til 400Gbit/s

Diodes er klar med PI6C59xxxxx serien af differentielle clock buffere, der understøtter Ethernet hastigheder på op til 400Gbit/s og er velegnede til datacentre og 5G basestationer (in english).

Diodes has announced the PI6C59xxxxx series of differential clock buffers. The series supports Ethernet speeds up to 400Gbit/s and are well-suited for high-performance applications such as data centers and 5G basestations.

The demand for network speeds operating from 25Gbit/s up to 400Gbit/s (known as the Terabit Ethernet, or TbE) is increasing, putting designers of switches and routers under pressure to maintain signal integrity in more challenging environments.

The PI6C59xxxxx series of differential clock buffers provides better signal margin while expanding the drive capability of all clock and data signals used in high-speed communications. It covers a wide number of speeds and technologies, as well as combinations of input and output configurations.

The devices in the PI6C59xxxxx series have been designed to increase the fanout of clock sources and improve clock and/or data distribution in communication applications operating between 1.5GHz and 6GHz. This covers 25G, 40G, 56G, 100G, and 400GbE, as demanded by a wide variety of applications where low jitter and fast rise/fall times are required.

The ultra-low additive jitter of the devices is around 10fs, to deliver improved jitter margins to maintain overall accuracy. All devices are available in the TQFN package outline, and provide good thermal conductivity in a small footprint. This is increasingly important for data center and basestation applications, where suppliers need increased power density, performance, bandwidth, and functionality.

With 13 variants in the PI6C59xxxxx series, it covers all of the main signaling technologies used in high-speed networking, including CML (current mode logic), LVDS (low voltage differential signaling), LVPECL (low voltage positive emitter coupled logic) and SSTL (stub series terminated logic), as well as LVCMOS. Configurations include 2, 4, 12, and 16-output for fanout buffers and data/clock buffers.

4/7 2019
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