Analog, mixed-signal

 

Timing-produkter til 56G/112G SerDes

Silcon Labs har udvidet firmaets timing/clocking produkter med nye serier, der retter sig mod 56G PAM-4 SerDes og kommende 112G serielle applikationer (in english).

Dette er en prøve. Silicon Labs has expanded its timing portfolio to meet the high-performance clocking requirements of 56G PAM-4 SerDes and emerging 112G serial applications. With this portfolio expansion, Silicon Labs is the only timing supplier to offer a comprehensive selection of clock generators, jitter attenuating clocks, voltage-controlled crystal oscillators (VCXOs) and XOs for 100/200/400/600G designs that satisfy sub-100 fs reference clock jitter requirements with margin.

Leading manufacturers of switch SoCs, PHYs, FPGAs and ASICs, including Broadcom, Inphi, Intel, MACOM, Marvell, MediaTek and Xilinx, are migrating to 56G PAM-4 SerDes technology to support higher bandwidth 100G+ Ethernet and optical networking designs. To meet the stringent requirements of 56G SerDes reference clocks, hardware developers often require clocks with sub-100 fs (typical) RMS phase jitter specifications. These designs typically use a mix of other frequencies for CPU and system

clocks. Silicon Labs is the first timing supplier to provide fully integrated clock IC solutions for 56G designs that integrate SerDes, CPU and system clocks into a single device.

In 56G applications, hardware developers often seek complete clock tree solutions guaranteeing sub-100 fs RMS phase jitter to ensure sufficient margin and de-risk product development. Silicon Labs’ new clock and oscillator products meet these stringent 56G SerDes requirements today, as well as the needs of emerging 112G serial SerDes designs that will ramp in data center and communications applications in the future. 

- Silicon Labs’ new clock generators, jitter attenuators and VCXO/XOs comprise the industry’s broadest portfolio of frequency-flexible, ultra-low-jitter timing devices for the latest 56G SerDes-based 100/200/400/600G communications and data center designs, says James Wilson, Senior Marketing Director for Silicon Labs’ timing products.
26/6 2018
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