FPGA, CPLD, ASIC og EDA

 

Microsemi klar med opdateret FPGA-designsuite

Microsemi annoncerer ny Libero SoC PolarFire v2.0 til design omkring firmaets kostoptimerede low-power mid-range FPGA'er (in english).

Microsemi Corporation has announced the availability of its Libero system-on-chip (SoC) PolarFire version 2.0 comprehensive design software tool suite, used for the development of the company's lowest power, cost-optimized mid-range PolarFire field programmable gate array (FPGAs) and supporting all PolarFire FPGA family devices and packages.

Microsemi’s Libero SoC PolarFire Design Suite provides a complete design environment for customers working on designs requiring high-speed transceivers and memories with low power consumption. It enables high productivity with its comprehensive, easy to learn, easy to adopt development tools and enables a design launching point for customers with key quick start demonstration designs for rapid evaluation and prototyping.


Several full design files for Libero SoC PolarFire targeting the company’s complementary PolarFire Evaluation Kit are also available, including JESD204B Interface, PCI Express (PCIe) Endpoint, 10GBASE-R Ethernet, digital signal processing (DSP) finite impulse response (FIR) filter and multi-rate transceiver demonstration, with additional reference designs planned over the coming months.

- Our Libero SoC PolarFire v2.0 release supports all of the PolarFire product family’s devices and packages, enabling customers to further leverage the high-performance capabilities of our lowest power, cost-optimized mid-range FPGAs for their designs, says Jim Davis, vice president of software engineering at Microsemi.

- Feature enhancements to best-in-class debug tool SmartDebug provide the ability to evaluate transceiver performance while modifying transceiver lane signal integrity parameters on the fly, and to evaluate the channel noise of the transceiver receiver through the eye monitor. In addition, the demonstration mode allows customers to evaluate SmartDebug features without connecting to a hardware board—a capability unique to Microsemi FPGAs. 

The enhanced design suite also includes significant runtime improvement for SmartPower, with a 4x speed up of invocation time and almost instantaneous switching between different views. In addition, Libero SoC PolarFire v2.0 introduces a brand new SmartDesign canvas with higher quality, higher speed of displaying nets and easier design navigation.

While Microsemi’s PolarFire FPGAs are ideal for a wide variety of applications within the communications, industrial and aerospace and defense markets, the new software provides new capabilities for high-speed applications, offering particular suitability for access networks, wireless infrastructure, and the defense and industry 4.0 markets.

Application examples include wireline access, network edge, wireless heterogeneous networks, wireless backhaul, smart optical modules, video broadcasting, encryption and root of trust, secure wireless communications, radar and electronic warfare (EW), aircraft networking, actuation and control.

With the release of Libero SoC PolarFire v2.0, Microsemi has added support for PolarFire MPF100, MPF200, MPF300 and MPF500 devices for all package options, enabling customers to design with all members of the PolarFire family. It also adds the MPF300TS-FCG484 (STD) device to Libero Gold License and introduces the MPF100T device supported by the free Libero Silver License.

Microsemi’s PolarFire FPGA devices provide cost-effective bandwidth processing capabilities with the lowest power footprint. They feature 12.7 Gbps transceivers and offer up to 50 percent lower power than competing mid-range FPGAs, and include hardened PCIe controller cores with both endpoints and root port modes available, as well as low power transceivers.

The company’s complementary PolarFire Evaluation Kit is a comprehensive platform for evaluating its PolarFire FPGAs which includes a PCIe edge connector with four lanes and a demonstration design. The kit features a high-pin-count (HPC) FPGA mezzanine card (FMC), a single full-duplex lane of surface mount assemblies (SMAs), PCIe x4 fingers, dual Gigabit Ethernet RJ45 and a small form-factor pluggable (SFP) module.
4/12 2017
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