Power, strømforsyning, EMC/ESD


Power MOSFETs i ny industristandard 'Source Down' pakningThe new package concept connects the source potential (instead of the drain potential) to the thermal pad. Along with the enabled new PCB layout possibilities.

Power MOSFETs i ny industristandard 'Source Down' pakning

Infineon lancerer de første OptimMOS MOSFETs baseret på det nye Source Down pakningskoncept, der leveres i en PQFN formfaktor på 3,3x3,3mm (in english).

Infineon Technologies is focusing on system innovation with enhancements on component level by addressing the challenges of modern power management designs. The so-called Source Down is the new industry standard packaging concept. The first wave of power MOSFETs launched in this new package is the OptiMOS TM 25 V in a PQFN 3.3x3.3 mm.

The device sets a new industry benchmark in MOSFET performance, reducing on-state resistance (Rds(on)) and offering superior thermal management capability to the marketplace. The product is well-suited for a wide range of applications such as drives, SMPS (including server, telecom, and OR-ing) and battery management.

The new package concept connects the source potential (instead of the drain potential) to the thermal pad. Along with the enabled new PCB layout possibilities, this helps achieving ever higher power density and performance.

Two different footprint versions are released – the Source-Down Standard-Gate and the Source-Down Center-Gate in a PQFN 3.3x3.3 mm package. The Source-Down Standard-Gate footprint is based on the current PQFN 3.3x3.3 mm pinout configuration.

The location of the electrical connection remains the same, simplifying the drop-in replacement of today's standard Drain-Down packages with the new Source-Down package. For the Center-Gate version, the gate-pin is moved to the center supporting easy parallel configuration of multiple MOSFETs.

With its larger drain-to-source creepage distance, it is possible to connect the gates of multiple devices on a single PCB layer. In addition, moving the gate connection to the center leads to a wider source area for improved electrical connection of devices.

This technology innovation results in major reduction of R DS(on) by up to 30 % compared to current technology. The thermal resistance between junction to case is also significantly improved compared to the current PQFN packages. Reduced parasitics, improved PCB losses, as well as superior thermal performance, add significant value to any contemporary engineering designs.
10/2 2020
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