TSMC's nye 16nm FinFET Plus proces giver markante fordele
TSMC har nu annonceret, at firmaets 16nm FinFET Plus (16FF+) procesteknologi nu er i såkaldt 'risk' produktion (in english).
TSMC has announced that its 16-nanometer FinFET Plus (16FF+) process is now in risk production. This enhanced version of TSMC’s 16FF process operates 40% faster than the company’s planar 20-nanometer system-on-chip (20SoC) process, or consumes 50% less power at the same speed. It offers customers a new level of performance and power optimisation targeted at the next generation of high-end mobile, computing, networking and consumer applications.TSMC’s 16nm process offers an extended scaling of advanced SoC designs and is verified to reach speeds of 2.3GHz with ARM’s “big” Cortex®-A57 in high-speed applications while consuming as little as 75mW with the “LITTLE” Cortex-A53 in low-power applications. It is making excellent progress in yield learning, and has achieved the best technology maturity at the same corresponding stage as compared to all TSMC's previous nodes.
- Our successful ramp-up in 20SoC has blazed a trail for 16FF and 16FF+, allowing us to rapidly offer a highly competitive technology to achieve maximum value for customers’ products, says TSMC President and Co-CEO, Dr. Mark Liu.
- We believe this new process can provide our customers the right balance between performance and cost so they can best meet their design requirements and time-to-market goals.
TSMC’s comprehensive 16FF+ design ecosystem supports a wide variety of EDA tools and hundreds of process design kits with more than 100 IPs, all of which have been silicon validated. Backed by the resources of the biggest design ecosystem in the industry, TSMC and its customers are starting intensive design engagements, paving the way for future product tape-outs, pilot activities and early sampling.
The 16FF+ process is on track to pass full reliability qualification later in November, and nearly 60 customer designs are currently scheduled to tape out by the end of 2015. Due to rapid progress in yield and performance, TSMC anticipates 16FF+ volume ramp will begin around July in 2015.
- TSMC 16FF+ process technology enables Avago to design highly optimised custom silicon solutions for networking applications in cloud datacenters and enterprise networks, says Hock Tan, President and CEO of Avago Technologies Limited.
- TSMC’s 16FF+ process technology in combination with Avago’s industry leading SerDes, memory, processor cores and design implementation techniques deliver unparalleled time-to-market, performance and power benefits to OEM customers.
- Sixteen-nanometer FinFET Plus technology provides compelling performance per watt advantages, enabling a myriad wave of market inflection points such as Internet of Things, 5G networks and software defined networks, says Tom Deitrich, Senior Vice President and General Manager for Freescale’s Digital Networking group.
- Powering the new virtualised network, a new family of Layerscape multicore processors using ARM and Power Architecture technologies will be Freescale’s first offerings to leverage this innovative process technology.
