FPGA-designsuite med 'mixed language' simulering

Microsemi lancerer Libero SoC v11.8 softwaren, der inkluderer en lang række markante udvidelser og forbedringer (in english).

In addition to the new software release, which includes significant enhancements such as mixed language simulation, best-in-class debugging capabilities and a new netlist viewer, the company is also introducing a free evaluation license enabling users to evaluate Microsemi’s flash-based FPGAs and SoC FPGAs.

Microsemi’s Libero SoC tool suite includes the Mentor Graphics ModelSim Simulator allowing line by line verification of hardware description language (HDL) code. Simulation can be performed at all levels: behavioral (pre-synthesis), structural (post-synthesis), and back-annotated, dynamic simulation. An easy-to-use graphical user interface enables quick identification and debug of problems.

Libero SoC v11.8 now includes ModelSim Microsemi Pro allowing customers to simulate in mixed language environments as well as 20 percent runtime improvement in recent versions of the tool.

- Our newly released Libero SoC v11.8 provides significant enhancements including ModelSim ME Pro, which provides mixed language simulation support for VHSIC Hardware Description Language (VHDL), Verilog and SystemVerilog. This enables customers to target a broad range of intellectual property (IP) designs without worrying about mixing languages, says Jim Davis, vice president of software engineering at Microsemi.

- It also includes the latest SmartDebug enhancements, such as the FPGA Hardware Breakpoint (FHB), a capability unique to Microsemi FPGAs. FHBs enable users to set breakpoints in their designs and step by clock cycle, providing significant visibility and enabling significant reduction in debug time.

While breakpoints have been used historically in embedded software, they can now be used to support FPGA logic debug functions. This increases productivity, usability and efficiency of FPGA designs, resulting in faster time to market for customers - particularly in the product validation phase, the longest cycle of product development.

These significant SmartDebug enhancements complement existing debug capabilities which offer a new approach to debug FPGA devices’ status, memory and Serializer/Deserializer (SerDes) transceivers without using an integrated logic analyzer (ILA).

Microsemi’s Libero SoC v11.8 is ideal for FPGA designs targeting applications within the aerospace, defense, security, communications, data center, industrial and automotive markets. It now includes a number of additional compelling features, including a new netlist viewer providing visibility into different internal structures, new constraints management features offering block flow and an input/output (I/O) advisor, 20 percent runtime improvements for its SmartTime user interface and Windows 10 operating system support.

In order to facilitate broad adoption, Libero SoC v11.8 also comes with a new 60-day evaluation license which can be used to evaluate Microsemi flash-based FPGA and SoC reference designs, tutorials and application notes.