Nye FPGA'er med transceivere

Altera lancerer nu to ny FPGA-familier med integrerede transceivere. Ny version af Quartus II softwaren, understøtter udvikling af transceiver FPGA'er og HardCopy ASICs (in english).

The Arria II GX, Stratix IV GT, and Stratix IV GX FPGAs and HardCopy IV GX ASICs utilize common transceiver technology and are supported by a common set of development tools that enable system designers to develop full system-on-chip (SoC) solutions. This portfolio delivers both FPGA solutions from 16K logic elements (LEs) to 530K LEs, and HardCopy ASIC solutions of up to 11.5 million ASIC gates.

The programmable fabric and integrated programmable transceivers provide designers with the flexibility needed to overcome unpredictable design requirements. Altera’s transceiver technology provides easy-to-use signal integrity features that accelerate product development, while consuming less power than competing solutions.

- Altera's expanded portfolio of transceiver FPGAs and HardCopy ASICs address the increasing market demand for a range of transceiver solutions. Since each application requires a unique set of features at specific performance, power, and price points, Altera developed this portfolio to provide optimal solutions to address a broad range of applications. These products offer superior signal integrity, the lowest jitter specifications, and broad high-speed I/O protocol compliance, alleviating the challenges facing designers of systems requiring transceivers, says Danny Biran, senior vice president of product and corporate marketing at Altera Corporation.

The highest performing FPGAs available, Stratix IV GT devices are also the industry’s first FPGAs to include integrated transceivers operating at 11.3 Gbps. The architecture is optimized specifically for 40G and 100G applications such as communications systems, high-end test equipment, and military communications systems. Stratix IV GT FPGAs have 24 transceivers operating at 11.3 Gbps, and an additional 24 transceivers operating at 6.5 Gbps, to deliver the industry's highest bandwidth available. The Stratix IV GT devices also offer up to 530K LEs, 20.3-Mbits internal RAM and 1,288 18 x 18 multipliers.

Arria II GX devices are the lowest power 3.75 Gbps transceiver FPGAs and are cost optimized for applications using mainstream protocols such as PCI Express (PCIe) and Gigabit Ethernet (GbE). They feature up to 16 3.75-Gbps transceivers, 256K LEs, and 8.5 Mbits of internal RAM. In addition, the Arria II GX FPGAs also support targeted protocols such as CPRI for LTE and WiMAX wireless infrastructure access equipment, GPON and XAUI for wireline infrastructure access and networking equipment, and triple-speed SDI for broadcast and other video processing equipment. A collection of reference designs and design examples accelerates the development of solutions using Arria II GX FPGAs.

The first Arria II GX device, the EP2AGX125, will ship in May 2009 with production devices scheduled for the fourth quarter of 2009. Budgetary pricing for the smallest device, the EP2AGX20, will start as low as $15 for 100K unit quantities in 2010.

New Quartus II software

Parallel with the the introduction of the transceiver FPGAs, Altera has announced the availability of Quartus II software version 9.0, the CPLD, FPGA and HardCopy ASIC development environment. The 9.0 version includes full support for Altera's portfolio of transceiver FPGAs and HardCopy ASICs. Enhanced features within this latest Quartus II development environment ensure customers can deliver their Altera solutions to market sooner and with reduced engineering expenses.

When designing with Quartus II software version 9.0, customers are equipped with a unified design environment supporting Altera's entire portfolio of CPLDs, FPGAs and HardCopy ASICs. The latest release includes support for Altera's newly announced Stratix® IV GT and Arria® II GX FPGAs.

- New SSN Analyzer Tool—Provides designer feedback on potential simultaneous switching noise (SSN) violations during pin assignments, enabling faster board design and improving signal integrity.

- Enhanced SOPC Builder—Quartus II software further extends productivity advantages with SOPC Builder's Data Sheet Generator for easier hand-off between hardware and software engineers. In addition, SOPC Builder's enhanced GUI now offers easier visualization of large systems.

- Metastability Analysis—Provides tools to auto-recognize potential metastability circuit issues, and to automate reporting of mean-time-between-failure (MTBF) values as an integrated part of the TimeQuest static timing analysis tool.

- Pin Planner Enhancements—A new Clock Network View now available within the pin planner allows designers to better manage clock resources, improving productivity and maximizing performance