Europæisk universitets-konsortium skal samarbejde om den næste generation af chips

Med imec som et centralt omdrejningspunkt er 26 europæiske universitets-grupperinger (dog ingen danske) gået sammen om forskning i chipteknologier, der går videre end transistorskalering, som man har kendt i mange årtier (in english).

Imec, the world-leading research and innovation hub in advanced semiconductor technologies, has launched a first of its kind consortium with 26 European university groups that will jointly work on the technology roadmap beyond CMOS scaling (CMOS 2.0). This initiative will focus on design automation and chip architecture research for the next generation of chips. 

The consortium will benefit from the NanoIC pilot line, turning academic insights into industry-focused innovations. In the future, similar consortia will be set up around advanced materials and alternative compute systems.

CMOS 2.0 refers to a new paradigm, introduced by imec, that expands the chipmaking toolbox beyond traditional transistor scaling and its associated scaling challenges. CMOS 2.0 allows for more design flexibility by exploiting fine-grain wafer stacking technology to improve on-chip connectivity and offer higher technology heterogeneity to the system. It will result in tailored chips comprising multiple 3D-stacked layers that fulfil smartly partitioned functions. In that way, CMOS 2.0 will provide advanced, versatile 3D stacked platforms that push the boundaries of compute performance.

Introducing this new paradigm will have profound implications on how computing architectures are designed and optimized for future workloads and applications. CMOS 2.0 is a key differentiator for the realization of next-generation energy efficient compute systems and is expected to impact a wide variety of applications from general purpose processors to High Performance AI Computing systems and even further for embedded AI applications at the edge.

This strategically important research requires cross-pollination between different areas of the ecosystem. Within imec's CMOS 2.0-consortium, 26 PhDs will be funded. The PhD students will stay at their home university, embedded in their research group, allowing them to tap into complementary fields of expertise and stimulate cross-fertilization. The participating universities and imec will jointly develop the necessary know-how that lays down the foundation of the next generation CMOS technology platforms and their associated compute architectures. Moreover, the collaboration will support workforce and skill development in Europe to meet current and future industry needs.

Sahar Sahhaf, Director Academic Partnership Development explains: 

- The attraction for the concept of CMOS2.0 is clear, but the obstacles are equally substantial. Leveraging the benefits in both connectivity and heterogeneous integration enabled by 3D wafer stacking will reshape every stage of design and chip architecture. It requires convergence of expertise, close collaboration, and coordination. It's the first time that imec brings together such a network of premium European university teams in a structured way to have guided contributions to the future semiconductor roadmap. We are excited to further connect academic inputs in our industry-driven programs to put Europe in the forefront of research on advanced computing technologies.

Mehdi Tahoori, Technical Director adds:

This university research consortium aims to infuse CMOS 2.0 technology to the entire design stack, from EDA all the way to system architecture. It aims to stimulate the broader research and academic community on various aspects of the CMOS 2.0 revolution. Imec plays a unique and crucial role by linking academic research to industry needs, and by extending the roadmap of technology scaling with CMOS 2.0.