Ny SoC verifikationsplatform fra Synopsys

Synopsys er klar med ny unified verfikationsplatform, der kan forkorte time-to-market markant for komplekse SoCs (in english).

Verification Continuum is built from Synopsys’ market leading and fastest verification technologies providing virtual prototyping, static and formal verification, simulation, emulation, FPGA based prototyping and debug in a unified environment with verification IP, planning and coverage technology. Verification Continuum introduces Unified Compile with VCS and Unified Debug with Verdi across the verification flow, speeding time to market by months for complex SoC designs.

- AMD’s advanced multi core Accelerated Processor Unit designs require a continuum of verification technologies working seamlessly together to meet growing hardware and software verification requirements, says Alex Starr, fellow & pre silicon solutions architect at AMD.
- Synopsys Verification Continuum represents an important new direction for the industry, and our initial evaluation of the technology indicates it can accelerate design schedules with a more efficient and scalable platform optimised for complex SoC verification and early software bring up.
 
The mobile and Internet of Things (IoT) markets are driving dramatic increases in SoC complexity and software content along with intensifying time to market pressure. To address these challenges, SoC teams require many verification technologies such as simulation, emulation and prototyping across the spectrum of pre silicon verification, post silicon validation and early software bring up.

Today engineers spend months of effort in design bring up and transition effort between disjointed technologies, further complicated by the need to debug across domains and to support large software teams.

To shorten SoC time to market, leading teams are adopting 'shift left' strategies with concurrent practices across pre silicon verification, post silicon validation and software bring up. Synopsys’ Verification Continuum enables these shift left strategies with best in class verification technologies unified with seamless design bring up, transition and debug throughout the flow.

Industry’s fastest verification engines

Synopsys’ Verification Continuum is built from the industry’s fastest verification engines including Virtualizer virtual prototyping, Verification Compiler static and formal technologies, VCS simulation, ZeBu emulation, HAPS FPGA based prototyping and Verdi3 debug. These best in class technologies provide the performance and capacity that industry leaders depend on to verify many of the world’s largest and most complex chips.

Unified compile with industry leading VCS

Verification Continuum features Unified Compile based on the mature VCS simulator front end, providing a robust simulation like user experience across the verification flow, that enables engineers to easily transition between simulation, static and formal verification, emulation,

FPGA based prototyping and debug as required by the verification task. Existing flows based on individual point tools require extensive setup for each tool in the flow, and weeks or months of effort to move a design between different tools based on varying language support or other requirements. Unified Compile with VCS eliminates this redundant work, saving months of effort in typical project schedules.

Unified debug with Verdi

Unified Debug based on Synopsys’ Verdi3 environment provides a consistent debug user experience across the verification flow, optimised with Verification Continuum technologies for even higher productivity. Verdi3 has long been recognised as the leading open debug platform, and as part of the Verification Continuum, it provides a single interface for multi domain debug across virtual prototyping, static and formal verification, simulation, emulation and FPGA based prototyping. Since bugs may exist on the boundary between traditional verification domains, Verdi3 also enables fully synchronised, mixed abstraction debug between SPICE, RTL, transactions and software.

Scalable FPGA based emulation and prototyping

As SoC complexity and software content increase, leading SoC development teams have concluded that commercial FPGA based hardware assisted verification is the best, most scalable approach to meet the growing demand for high performance platforms for early software bring up and SoC verification.

Verification Continuum integrates FPGA based emulation and prototyping seamlessly into mainstream verification flows, helping to save weeks to months in design bring up time compared with earlier approaches. Verification Continuum’s Unified Compile technology has been architected to support FPGA based verification platforms, delivering up to 3X faster compile time for Synopsys’ ZeBu Server 3 emulation system.

- The Verification Continuum requires an optimised software flow combined with the highest performance, highest capacity emulation and prototyping hardware, says Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.

- Xilinx has raised the bar again with our Virtex UltraScale devices, offering the largest 20nm FPGA in the industry, the XCVU440. We are working closely with Synopsys to optimise our Vivado Design Suite flow to address the unique requirements of hardware assisted verification users.
 
- Synopsys’ Verification Continuum, developed in close collaboration with market leaders, will enable a new era of SoC verification for the industry, says Manoj Gandhi, senior vice president and general manager of the Verification Group at Synopsys.

- The significant verification R&D investments Synopsys has made over the past two years are already showing promising early results towards helping customers reduce time to market by months for advanced SoC designs.
 
Early availability is scheduled for December 2014, with general availability in 2015.