Unik system-level III-V chiplet integration på Si-CMOS
Imec videreudvikler deres 300mm RF silicon interposer til en unik system-level platform for heterogen integration af III-V chiplets på Si CMOS (in english).
Imec, a world-leading research and innovation hub in advanced semiconductor technologies, is evolving its 300mm RF silicon interposer into a system-level platform for the heterogeneous integration of III-V chiplets on Si-CMOS.
By uniquely combining high-density embedded capacitors, a scalable modeling framework for passive components, and laser-assisted bonding for III-V chiplet assembly, the platform lays the foundation for next-generation wireless (mmWave and sub-THz) systems, as well as RF-grade signal handling for ultrafast data center applications.
As wireless systems move into mmWave and sub-THz frequencies, and electronic and photonic interfaces in data centers are increasingly reaching their limits, it is becoming more difficult to deliver high-performance signal handling without driving up system integration complexity, cost, power consumption, and footprint.
A promising solution is to combine the superior gain, power, and efficiency of III-V materials - such as InP, GaAs, and GaN - with the scalability and cost efficiency of Si-CMOS technology.
Chiplet-based heterogeneous integration on a high-performance RF silicon interposer makes this possible: it keeps performance-critical functions in compact III-V chiplets, while the interposer provides low-loss interconnects and hosts the remaining passive components.
Imec has been steadily advancing such a platform. In 2024, it demonstrated seamless InP chiplet integration on a 300mm RF silicon interposer with negligible insertion loss at 140GHz. In 2025, it extended the platform’s record-low insertion loss up to 325GHz.
Now, imec expands this platform with three new, complementary enablers: high-density embedded capacitors, a scalable modeling framework for passive components, and laser-assisted bonding for III-V chiplet assembly.
A 10-to-100-fold increase in MIMCAP capacitance density for high compactness and cost efficiency
- A key lever to reduce III-V chiplet size and cost is the offloading of passive components - such as decoupling capacitors - onto the RF silicon interposer, says Xiao Sun, principal member of technical staff at imec, and he continues:
- In a paper presented at this year’s IMS/RFIC conference, we demonstrate how combining this offloading approach with a new MIMCAP architecture enables a 10-to-100-fold increase in capacitance density compared to typical on-chip capacitors in III-V technologies.
This supports more compact and cost-efficient system designs and improves power delivery for mmWave and sub-THz wireless systems as well as high-speed data center applications.
Imec’s new MIM capacitor (MIMCAP) architecture combines a high-k aluminum-hafnium-oxide dielectric with three-dimensional (3D) oxide-stud structures in the back-end-of-line (BEOL).
A modeling framework for predictable design of passive components up to sub-THz frequencies
Complementing this effort, imec recently presented a modeling framework for RF interposer passives, validated up to the sub-THz regime (around 300GHz). Imec’s model enables designers to accurately predict circuit performance as geometries change, without needing to re-simulate or measure every variation, significantly reducing development time.
To date, imec’s framework has focused on transmission line performance – but lays the foundation for a comprehensive design library that is being extended to other passive components, including inductors and MIMCAPs.
Finally, imec demonstrated the use of laser-assisted bonding to integrate III-V chiplets onto its RF silicon interposer, enabling assembly of chiplets on a complex, passives-rich stack without compromising thermal budgets, or damaging temperature-sensitive interposer layers.
