Værktøj til design af højhastigheds chip-to-chip links

Agilent Technologies’ lancerer værktøj, der håndterer nogle af de store udfordringer i forbindelse med design af chip-to-chip links (in english).

In modern chip-to-chip links, this metric has become less relevant because it doesn’t take holistic effects of the end-to-end link into account. Most important, the effect of the equalizer in the receiver is ignored. The metric that matters today is the post-equalization eye opening.

The integration of Agilent’s Controlled Impedance Line Designer and the existing Channel Simulator in ADS rectifies this situation by letting engineers see a set of eye openings that result from sweeping through the pre-layout design parameters (e.g., line width).

To ensure accurate calculation of the transmission line characteristics, the software automatically employs a fast, cross-sectional (2D) electromagnetic field solver. The dielectric layers are modeled using the frequency-dependent Svensson/Djordjevic permittivity, which ensures both accuracy and delay causality. The metal layer model accounts for conductivity, skin effect, and top and bottom surface roughness.

The Controlled Impedance Line Designer also includes a provision to determine the effect of manufacturing variation on input parameters, such as thickness on the output parameters (e.g., impedance).

- This new approach brings line design into the multigigabit era, explains Colin Warwick, product manager for high-speed digital design at Agilent EEsof EDA.
- The whole point of the signal processing in the I/O of modern chips is to allow you to use lower-cost materials and yet still open the eye. For the first time, engineers can easily explore those interactions and trade-offs.

Altoo Measurement Science ApS
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Phone: 70 13 15 15
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