Interface IP'er til TSMC' 20nm teknologi
Synopsys introducerer nu en serie af interface IP'er til TSMC’s 20SoC proces.
Synopsys has announced the availability of a range of DesignWare Interface IP on TSMC’s 20 nanometer (nm) system on chip (SoC) process. The silicon-proven Synopsys DesignWare USB, DDR, PCI Express and MIPI PHY IP on TSMC’s 20SoC process reduces risk for designers who need to implement the latest interface IP standards in their SoCs and want to take advantage of 25 percent lower power consumption or a 30 percent performance improvement offered by TSMC’s 20SoC process compared to TSMC’s 28nm process.The DesignWare IP portfolio is designed to achieve high yield by meeting the requirements of advanced manufacturing design, such as adhering to double patterning layout rules.
- TSMC and Synopsys have a long history of collaboration on leading edge process technology migration, delivering high quality, proven IP that helps our mutual customers speed their time to volume production, says Suk Lee, TSMC senior director, design infrastructure marketing division.
- The availability of Synopsys’ high quality IP portfolio for our 20SoC customers provides a low risk path to implementing proven IP while reducing SoC power consumption.
As designs migrate to smaller process nodes, such as 20nm and 16nm FinFET, the technology challenges to extend Moore’s Law become increasingly complex. TSMC has implemented double patterning mask technology on its 20SoC process utilising two photo masks, each with half of a pattern, to enable printing of images below the node’s minimum spacing design rules.
Synopsys’ development of DesignWare IP at 20nm focused on minimising yield and manufacturability issues while adhering to the standards’ specifications, as well as TSMC’s advanced layout and design rules for manufacturability with double patterning technology.
- As the leading provider of physical IP with more than 80 test chip tape outs in 20 and 28nm, Synopsys is focused on developing IP in the most advanced process nodes to help designers take full advantage of the processes speed and power characteristics while implementing high-quality, proven IP, says John Koeter, vice president of marketing for IP and systems at Synopsys.
- By offering a broad portfolio of IP for the 20nm process, Synopsys enables designers to more easily meet their goals of creating differentiated products with less risk and faster time to volume production, while also reducing the risks associated with moving to the 16nm FinFET process.
