Synopsys lancerer 3D IC initiativ

Synopsys bag nyt initiativ, der sigter på at accelerere design af stacked multidie chip-implementeringer (in english).

As part of its 3D-IC initiative, Synopsys is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.

3D-IC technology complements conventional transistor scaling to enable designers to achieve higher levels of integration by allowing multiple die to be stacked vertically, or in a side by side '2.5D' configuration on a silicon interposer. 3D-IC integration uses through silicon via (TSV) technology, an emerging interconnection technology that will replace the traditional wire bonding process in chip/wafer stacking. The use of TSVs can increase inter-die communication bandwidth, reduce form factor and lower power consumption of stacked multi-die systems.

- As 2D scaling becomes impractical, 3D-IC integration becomes the natural evolution of semiconductor technology; it is the convergence of performance, power and functionality, says Phil Marcoux, managing director at PPM Associates.

- Some of the benefits of 3D-IC integration, such as increasing complexity, improved performance, reducing power consumption and decreasing footprints, are proven and readily understood. Other reported benefits, such as improving time to market, lowering risk and lowering cost, still need to be realised before 3D-IC integration becomes a commercially viable alternative to traditional 2D architectures. The availability of Synopsys’ silicon proven EDA and IP solutions is an important contribution to deploying 3D-IC integration technology in the semiconductor industry.

Synopsys’ 3D-IC initiative begins at the semiconductor device level. Multi-die stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change causes material stress due to thermal mismatch, leading to silicon deformation and affecting transistor performance.

Furthermore, TSVs, microbumps and other solder bumps produce a permanent stress in the zone around them. Synopsys’ Sentaurus Interconnect TCAD tool analyses these effects and models the TSVs in the die stacks, enabling performance and reliability optimisation. Semiconductor companies, such as foundries, use modeling results to create design rules specific to 3D-IC integration to ensure manufacturability and reliability.