Lattice opdaterer FPGA designsuite

Lattice introducerer ny opgradering af ispLEVER FPGA designsuiten (in english).

Lattice Semiconductor Corp. has announced the immediate availability of Service Pack 2 for Version 7.2 of its ispLEVER FPGA design tool suite.  SP2 is a particularly important update for users of LatticeECP3 devices, and also includes support for new LatticeXP2 devices.

- Service Pack 2 further expands the breadth of Lattice product design support.  More specifically, this important update allows users of ECP3-70 and ECP-95 devices to design with even greater confidence that the board-level behaviour of their design, such as simultaneous switching output noise (SSO), power and timing, will match what the tools report. SP2 also boosts DSP application performance in the LatticeECP3 devices, says Mike Kendrick, Lattice’s Manager of Software Product Planning.  Updated Support for the

LatticeECP3 FPGA Family

Design support for the LatticeECP3 FPGA Family was first made available in the ispLEVER 7.2 SP1 design tool suite.  Service Pack 2 updates the device values to production characterized silicon for the LatticeECP3-70 and ECP3-95 devices. 

With SP2, static timing analysis, power and SSO will report results that even more accurately reflect the behaviour of the actual production device.  Moreover, PCS/SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behaviour. 

The sysDSP block support also has been enhanced to include higher performance modes of primitive blocks targeted at specific applications, such as FIR filters, decimators, interpolators, matrix multiplication and video applications.  These modes are made possible by the enhanced cascade support in the LatticeECP3 devices’ sysDSP architecture.

Service Pack 2 also supports the recently announced industrial temperature qualified, non-volatile LatticeXP2 devices that are available now in low-cost, small-footprint BGA or QFP packaging.