Komplet designflow til 65nm designs

TSMC lancerer integreret 'sign-off' flow til 65nm designs, der kan reducere designtiden og forbedre 'tape-out' kvaliteten (in english).

The worlds largest chipfoundry, TSMC (Taiwan Semiconductor Manufacturing Company), has unveiled the first foundry-specific Integrated Sign-Off Flow at its North American Technology Symposium in San Jose, CA. The new flow is available now for 65nm designs.

Integrated Sign-Off Flow is an automated RTL to GDSII chip implementation flow that tightly integrates all process-specific items including pre-qualified library and IP, selected EDA tools, production-quality flow, advanced design methodology, and TSMC foundry technology files that have been proven and refined over hundreds of applications.

With embedded TSMC design know-how and sign-off recommendations, the new flow utilises pre-qualified EDA toolsets from multiple vendors and leverages industry-proven TSMC Reference Flow methodology.

The Integrated Sign-Off Flow, targeting initially at 65nm process node with planned extensions into other process technology nodes, supports advanced design techniques for low power and Design-For-Manufacturability (DFM). It includes executable scripts for complete flow automation and EDA tool queuing system support.

With validated libraries and IP, qualified EDA tools, full set of proper technology files, and automated installation scripts, Integrated Sign-Off Flow significantly shortens the time it normally takes design team to set up the design environment and flow before starting the design project. The built-in advanced design methodology and proven sign-off scripts further shortens the design cycle, and improves tape-out quality.

- The ability to reduce design setup effort and design cycle time clearly result in design cost reduction, and this is one of the key objectives of the recently launched TSMC Open Innovation Platform, explains ST Juang, Senior Director of Design Infrastructure Marketing at TSMC.

- If we can lower design costs, we can help eliminate a major source of profit erosion that impacts all ecosystem parties, including our customers, our EDA partners and, of course, our own foundry services. This Integrated Sign-Off Flow represents a highly collaborative effort to increase reuse and reduce engineering waste.

The TSMC 65nm Integrated Sign-Off Flow is available now in limited release and at no charge to selective customers during Q2 2009. General release to other customers is targeted for Q3 2009.